1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device.
2. Description of the Related Art
A conventional method of fabricating an MESFET (MEtal Semiconductor Field Effect Transistor) is disclosed in III-C Device Fabrication in P1659 and in FIG. 9 in P1660 of the following Document 1.
Document 1: IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 8, AUGUST 1998, xe2x80x9c0.2 xcexcm Fully-Self-Aligned Y-Shaped Gate HJFET""s with Reduced Gate-Fringing Capacitance Fabricated Using Collimated Sputtering and Electroless Au-Platingxe2x80x9d, P1559 to P1660 (FIG. 9)
In Document 1, a technique related to a self-aligning method for forming SiO2 side walls by using side faces of an SiO2 insulating film and forming a gate electrode by using the side walls as a mask is described.
The technique is characterized in that the distance between an n+ cap layer and a gate electrode is adjusted by a side etching amount at the time of etching the n+ cap layer.
Common processing techniques related to gate formation are, except for the self aligning method, a lift-off method using a photoresist and an etching method using a dummy gate which are disclosed in the following Document 2.
Document 2: Ralph E. Williams, ARTECH HOUSE, xe2x80x9cGallium Arsenide Processing Techniquexe2x80x9d, P270 to P284, Chapter 12-3 GATE FABRICATION
The method of fabricating a semiconductor device described in Document 1 has, however, the following problems.
1. Since the side etching amount of the n+ cap layer (hereinbelow, called xe2x80x9cn+ layerxe2x80x9d) fluctuates according to etching conditions, the state of the n+ layer, and the like, it is extremely difficult to adjust the distance between the n+ layer and the gate electrode to a predetermined value.
2. Since the side faces of the n+ layer are exposed, it is feared that the gate electrode and the n+ layer are in contact with each other. The problem can occur due to a deviation (migration) of a vapor deposition position at the time of forming the gate electrode and wafer in-plane dependency of an incident angle of vapor deposition of a metal for forming the gate electrode.
3. Since Lsg (distance between the n+ layer on the source electrode side and the gate electrode) and Lgd (distance between the gate electrode and the n+ layer on the source electrode side) become equal to each other, an asymmetrical FET cannot be manufactured. The asymmetrical FET is used, for example, in the case where the source resistance is desired to be reduced or in the case where the withstand voltage between the gate and drain is desired to be improved.
On the other hand, like the method of fabricating a semiconductor device described in Document 2, in the case of forming a gate by patterning a resist, the minimum values of Lsg, Lgd, and Lg (gate length) are determined by the performances (especially, resolution) of an exposing device. In the case of increasing the packing density of a semiconductor device by making the pattern finer, a higher performance exposing device is required and it causes a rise in fabrication cost.
The invention has been achieved by considering the problems as described above and its object is to provide a method of fabricating a semiconductor device, capable of forming a pattern more finely and more variously without depending on the performance of an exposing device. It is another object of the invention to provide a method of fabricating a semiconductor device, capable of adjusting the distance between patterns with high accuracy while preventing short-circuiting between the patterns.
In order to achieve the objects, according to a first aspect of the invention, there is provided a method of fabricating a semiconductor device, including: a step of forming a first layer on a substrate; a step of forming a second layer on the first layer; a step of forming a recess from which the first layer is exposed by removing a part of the second layer; a step of forming an insulating film covering the surface of the second layer, and an inner wall face and a bottom face of the recess; a step of forming a mask (film for etching guard) by depositing a material different from the material of the insulating film onto the insulating film from a direction which forms a predetermined angle with a direction of a normal line of the surface of the insulating film; a step of performing anisotropic etching on the insulating film exposed from the mask from the direction of the normal line of the surface of the mask; a step of removing the mask; and a step of filling the recess with a metal material.
According to the fabricating method, in the bottom face of the recess, a region in which a mask is not formed and from which the insulating film is exposed is obtained. Only the insulating film in the exposed region is removed by anisotropic etching. Since the recess is filled with a metal material, the metal material and the first layer are electrically connected to each other, and the metal material and the second layer are electrically completely insulated from each other by the insulating film.
When an opening width and a depth of the recess after the insulating film is formed are W and D, respectively, the predetermined angle in the step of forming the mask is preferably adjusted to a value larger than a obtained from the following equation.
xcex1=tanxe2x88x921(W/D)
By adjusting the angle of deposition in such a manner, the depositing material does not reach the bottom face of the recess at the time of forming the mask. As a result, the mask is not formed on the entire bottom face of the recess and the insulating film is exposed.
When an opening width and a depth of the recess after the insulating film is formed are W and D, respectively, the predetermined angle in the step of forming the mask may be adjusted to a value smaller than xcex1 obtained from the following equation and larger than zero.
xcex1=tanxe2x88x921(W/D)
By adjusting the angle of deposition in such a manner, the depositing material does not reach a part of the bottom face of the recess at the time of forming the mask. As a result, a region in which the mask is not formed and from which the insulating film is exposed is obtained in the bottom face of the recess. The insulating film exposed in the recess is removed by anisotropic etching. By filling the recess with a metal material, the metal material and the first layer are connected to each other. In such a manner, a circuit pattern connecting the metal material and the first layer is made finer in accordance with the size of the exposed range of the insulating film in the recess, that is, the range in which the mask is not formed. The range in which the mask is not formed is enlarged or reduced by adjusting the angle of deposition. By properly adjusting the angle of deposition, the finer circuit pattern is therefore realized.
According to a second aspect of the invention, there is provided a method of fabricating a semiconductor device, comprising: a step of forming a first layer on a substrate; a step of forming a second layer on the first layer; a step of forming a first recess and a second recess from which the first layer is exposed by removing a part and another part of the second layer; a step of forming an insulating film covering the surface of the second layer, and an inner wall face and a bottom face of each of the first recess and the second recess; a step of forming a first mask on the insulating film positioned between the first recess and the second recess; a step of forming a second mask by depositing a material different from the material of the insulating film onto the insulating film and the first mask from a first direction which forms a predetermined first angle with a direction of a normal line of the surface of the insulating film; a step of forming a third mask by depositing a material different from the material of the insulating film onto the insulating film and the first mask from a second direction which forms a predetermined second angle with a direction of a normal line of the surface of the insulating film; a step of performing anisotropic etching on the insulating film exposed from the second mask and the third mask from directions of the normal lines of the surfaces of the second and third masks; a step of removing the first, second, and third masks; and a step of filling the first and second recesses with a metal material.
According to the fabricating method, at the time of forming the second mask (first film for etching guard) and at the time of forming the third mask (second film for etching guard), the depositing material can be shielded by the first mask (film for guarding depositing material) so as not to deposit the depositing material in a predetermined range. For example, at the time of forming the second mask, the depositing material is allowed to reach a part of the bottom face of the first recess but is not allowed to enter the second recess. At the time of forming the third mask, the depositing material is allowed to reach a part of the bottom face of the second recess but is not allowed to enter the first recess. By properly adjusting the angle of deposition at the time of forming the second mask and the angle of deposition at the time of forming the third mask, an independent circuit pattern can be formed in each of the first and second recesses.